1. Technical Field
The present invention relates to semiconductor memory devices, and in particular to semiconductor memory devices and sense amplifier control circuits thereof that can improve power serviceability of sensing power drivers, as well as improve sensing speed of bit line sense amplifiers by selectively connecting at least two sensing power drivers of one block to common sensing power lines.
2. Description of the Background Art
In general, methods for supplying sensing power RTO and /S to a sense amplifier may be classified as a method for driving a word line using a metal strap or a method for driving a word line using a sub-word line.
The former method was suggested in early development stages of semiconductor memory devices. Here, the sensing power is coupled to a sense amplifier outside a cell array block according to a block select address. In this method, power serviceability is decided according to a magnitude of the sensing power RTO and /S existing outside a memory cell array. According to this method, one sensing power RTO and /S exists in a block controlled according to the block select address.
The latter method has been more recently used. Here, sensing power drivers are aligned in sub-holes formed in the regions where sub-word line array regions and a sense amplifier array block cross one another between memory cell array blocks, and the sensing power RTO and /S is controlled according to sensing power supply control signals RTOEN and /SEN including a block address.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device for supplying the sensing power RTO and /S of a bit line sense amplifier to a bit line sense amplifier array block.
Referring to FIG. 1, a plurality of memory cell array blocks 1 are aligned in one bank in a matrix-type configuration. Bit line sense amplifier array blocks 2a and 2b are connected to both side ends of the memory cell array blocks 1. Sensing power drivers 3a, 3b, 3c and 3d for supplying the sensing power RTO and /S to the bit line sense amplifier array blocks 2a and 2b are aligned in each sub-hole. Sensing power supply control signal lines RTOEN0 and /SEN0, which supply sensing power supply control signals RTOEN and /SEN for controlling the sensing power drivers 3a, 3b, 3c and 3d, are aligned between the memory cell array blocks 1. Sensing power lines RTO0 and /S0 that supply the sensing power RTO and /S are driven according to the sensing power drivers 3a, 3b, 3c and 3d and are coupled to the bit line sense amplifier array blocks 2a and 2b are positioned between the sensing power supply control signal lines RTOEN0 and /SEN0.
As illustrated in FIG. 2, the sensing power driver 3a includes NMOS transistors NM1-NM3 controlled according to a bit line precharge control signal BLP, for precharging and equalizing the sensing power lines RTO0 and /S0 to a precharge voltage VBLP and a PMOS transistor PM1 controlled according to the sensing power supply control signal RTOEN0, for selectively transmitting an external power voltage VEXT to the sensing power line RTO0. The sensing power driver 3a also includes an NMOS transistor NM4 controlled according to the sensing power supply control signal /SEN0, to selectively connect the sensing power line /S0 to a ground.
The operation of the conventional sensing power driving circuit of the bit line sense amplifier are now explained.
The sensing power drivers 3a, 3b, 3c and 3d are aligned in the sub-holes formed in the regions where sub-word line array regions 4a and 4b and the sense amplifier array blocks 2a and 2b cross one another. The sensing power drivers 3a, 3b, 3c and 3d are controlled according to the sensing power supply control signals RTOEN0, RTOEN1, /SEN0 and /SEN1.
For example, when an i-th word line WLi of the memory cell array block 1 of FIG. 1 is selected, the bit line sense amplifier array blocks 2a and 2b, which are positioned at both side ends of the memory cell array block 1, sense and amplify data in a read or write operation. Here, the sensing powers RTO0, /S0, RTO1 and /S1 of the bit line sense amplifier array blocks 2a and 2b for reading or writing data of the selected memory cell array block 1 are respectively controlled according to the sensing power supply control signals RTOEN0, /SEN0, RTOEN1 and /SEN1. That is, when the i-th word line WLi is enabled, the sensing power supply control signals RTOEN0, /SEN0, RTOEN1 and /SEN1 are enabled according to the block select address.
When the sensing power supply control signals RTOEN0, /SEN0, RTOEN1 and /SEN1 are enabled, the PMOS transistor PM1 and the NMOS transistor NM4 are turned on according to the arrangement of FIG. 2, thereby supplying the external power voltage VEXT and the ground voltage VSS to the sensing power lines RTO0 and /S0, respectively.
Because the NMOS transistors NM1-NM3 have been already turned on according to the bit line precharge control signal BLP, the sensing power lines RTO0 and /S0 were precharged to the precharge voltage VBLP.
Therefore, the sensing lines RTO and /S are aligned in the sub-holes, and driven by the sensing power driver 3a controlled according to the sensing power supply control signals RTOEN0, /SEN0, RTOEN1 and /SEN1. As a result, when a sub-hole area is decreased due to reduction of the sense amplifier array blocks and the sub-word line regions according to high integration of the semiconductor memory device, a size of the sensing power drivers is also reduced, which results in low driving capacity.
According to one aspect, the disclosed device may be a semiconductor memory device that may include a plurality of memory cell array blocks aligned in a matrix-type configuration and a plurality of sense amplifier array blocks for sensing and amplifying data stored in the respective memory cell array blocks. The disclosed device may also include a plurality of sensing power drivers for supplying sensing power to the respective sense amplifier array blocks according to sensing power supply control signals and a plurality of switches for commonly connecting output terminals of at least two sensing power drivers to common sensing power lines according to the sensing power supply control signals.
In such an arrangement, the sensing power supply control signals may be generated using block select address signals. Additionally, the switches may be formed in sub-holes.